1. Field of the Invention
The present invention relates to a delay circuit and a method for delaying a logic signal having two logic levels, high and low levels, and relates in particular to a technology for suppressing the dependence of the delay time on source-voltage.
2. Description of the Related Art
Conventionally, in semiconductor apparatuses, delay circuits are used for obtaining timing for signals that are necessary for operating various circuits.
FIG. 16 shows an example of a circuit structure of a delay circuit according to the conventional technology.
The circuit shown in the diagram is constructed by forming an inverter chain using a plurality of inverters JV1˜JV4, and connecting an n-MOS transistor JN1˜JN4 between the output section of each of the inverter JV1˜JV4 and the ground. The gate terminals of the n-MOS transistors JN1˜JN4 are connected to the output section of the respective inverters JV1˜JV4, and the source and drain of the n-MOS transistors JN1˜JN4 are connected to the ground.
According to the delay circuit based on the conventional technology, because the n-MOS transistors JN1˜JN4 form MOS capacitors and capacitive loads are connected to each of the inverters, changes in the output signals from each inverter are successively moderated, thereby creating delays in the signal that passes through the delay circuit.
However, from the viewpoints of decreasing voltage resistance caused by microsizing of device structures achieved in recent years, and the desire to lower power consumption, it has become customary to operate internal circuits at low voltages. However, according to the delay circuit in the conventional technology described above, when the source voltage is decreased, delay times are increased excessively relative to the delay times in normal logic circuitries, resulting in a problem that the timing relationships are not satisfied for every signal.
This problem will be explained in detail below.
In semiconductor apparatuses such as DRAMs, address signal lines inside the decoder, for example, are provided over a long distance and such wiring itself exhibits parasitic resistance and parasitic capacitance. FIG. 17 shows such a signal line SL and a driver D (inverter) for driving the signal line. At the forward end of the signal line SL, the input section of a logic gate such as NAND circuit is connected. In this diagram, when sending a signal from the driver D to the logic gate, the driver D drives the parasitic load associated with the signal line SL. In this case, the signal level in the signal line SL varies according to a time constant determined by the parasitic resistance R of the signal line SL, the output resistance of the driver itself (i.e., on-resistance of the driving transistor) and the parasitic capacitance C of the signal line SL.
Here, although the on-resistance of the driving transistor comprising the driver D exhibits source-voltage dependency, and increases in proportion to the square of the source voltage when the source voltage drops, the parasitic resistance of the signal line does not exhibit source-voltage dependency. Generally, therefore, for those circuitries in which parasitic resistance of wiring represents the load, delay time for signals shows a tendency not to depend extensively on the source voltage.
In contrast, in the case of the delay circuit shown in FIG. 16, because the wiring connected to the output section of each inverter is short, wiring resistance does not exist in essence, resulting that the resistance component, that includes the MOS capacitance and contributes to the time constant, is dominated by the on-resistance of the transistor comprising each inverter. For this reason, as shown in FIG. 18, the conventional delay circuits exhibit higher source-voltage dependency compared with ordinary logic circuits so that the delay times become excessive as the source voltage drops. The result is a shift in timing between the signal transmitted through the internal logic circuits and the signal transmitted through the delay circuit, which can lead to occasional erroneous operation of those circuits that depend on timely receiving of such signals.